1. Field of the Invention
The present invention refers to a memory device, and particularly to a memory device with a data stub bus topology (DQ stub bus topology).
2. Description of the Related Art
In the following, an example for a prior art memory device with a data stub bus topology will be discussed in more detail with reference to FIG. 1. In the example shown in FIG. 1, the memory device comprises a first memory module 100 and a second memory module 102. The illustrated memory modules 100 and 102 are, for example, DIMMs (DIMM=Dual Inline Memory Module). The two memory elements 104 and 106, for example DRAMs, are shown exemplarily in FIG. 1, arranged in the first memory module 100. Further, as example, two memory elements 108 and 110, such as also DRAMs of the second memory module 102 are shown.
The memory device further comprises a controller 112, by which reading in/reading out of data to/from the memory elements 104 to 110 of the memory modules 100 and 102 is controlled. Therefore, the controller 112 is coupled to further elements of a data processing means via connections, not shown in FIG. 1, initiating access to one or several of the memory elements. Further, the memory device comprises means 114 for providing a read clock (read clock generator), connected to further elements, such as a phase lock loop providing the requested signals for generating and providing the read clock, respectively, via a connection, also not shown in FIG. 1.
The memory modules 100, 102, the controller 112 and means 114 are connected via bus systems for data exchange and data transfer, respectively, that will be described in more detail below.
In the illustrated embodiment, the memory device according to FIG. 1 comprises a data bus (DQ) comprising a first sub-data bus 116 and a second sub-data bus 118. The first sub-data bus 116 comprises a first portion 116a extending from the controller 112 to a branch 116b. A second portion 116c of the first sub-data bus 116 extends from the branch 116b to the memory element 104 in the first memory module 100. A third portion 116d of the first sub-data bus 116 extends from the branch 116b to the first memory element 108 in the second memory module 102. The second sub-data bus 118 comprises a first portion 118a extending from the controller 112 to a branch 118b. A second portion 118c of the first sub-data bus 118 extends from the branch 118b to the second memory element 106 in the first memory module 100. A third portion 118d of the second sub-data bus 118 extends from the branch 118b to the second memory element 110 in the second memory module 102.
Further, a read clock bus is provided, comprising a first sub-read clock bus 120 and a second sub-read clock bus 122. As can be seen in FIG. 1, a first portion 120a of the first sub-read clock bus 120 extends from the controller 112 to a first branch 120b. A second portion 120c of the first sub-read clock bus 120 extends from the branch 120b to the first memory element 104 in the first memory module 100. A third portion 120d of the first sub-read clock bus 120 extends from the first branch 120b to a second branch 120e. A fourth portion 120f of the first sub-read clock bus 120 extends from the second branch 120e to the first memory element 106 in the second memory module 102. A fifth portion 120g of the first sub-read clock bus 120 extends from the second branch 120e to the read clock generator 114. A first portion 122a of the second sub-read clock bus 122 extends from the controller 112 to a first branch 122b. A second portion 122c of the second sub-read clock bus 122 extends from the branch 122b to the second memory element 106 in the first memory module 100. A third portion 122d of the second sub-read clock bus 122 extends from the first branch 122b to a second branch 122e. A fourth portion 122f of the second sub-read clock bus 122 extends from the second branch 122e to the second memory element 110 in the second memory module 102. A fifth portion 122g of the second sub-read clock bus 122 extends from the second branch 122e to the read clock generator 114.
The mode of operation of the memory device illustrated in FIG. 1 is such that when reading data from the memory elements of the memory modules, the data will be provided on the respective data bus 116 or 118, and according to the read clock provided by the read clock generator 114 on the read clock bus 120 or 122, provided to the controller 112.
When writing data to the memory modules 100 or 102, the data to be written will be placed on the data buses 116 and 118, respectively, by the controller 112, and at the same time a write clock bus, not shown in FIG. 1, is provided, extending from the controller 112 to each of the memory elements 104 to 110. Concurrently with providing data to the data bus the respective clock signals will be provided to the write bus, so that when writing data to the memory elements 104 to 110 the data on the data bus as well as the clock signal on the write clock bus are applied substantially concurrently to a chosen memory element, i.e. between the data to be written on the data bus 116 and 118, respectively, and a write clock, no time delay can be recognized at the memory element to be written to.
The situation is different when reading data, and here, problems occur with the memory system described in FIG. 1, that are only very difficult to solve. As has been mentioned above, the read clock serves to read the data output by the memory elements into the controller. A problem is the implementation of the read clock bus in the DQ stub bus topology illustrated in FIG. 1, since here, as can easily be seen, a topology asymmetry between the topology of the data bus (DQ-bus) and the topology of the read clock buses exists, which leads to a delay between the read data and the read clock at the controller. The mentioned asymmetry is that the data bus and the read clock bus extend with different lengths through the memory system. While the buses along the portions 116a to 116d and 120a to 120f and along the portions 118a to 118d and 122a to 122f, respectively, are parallel, the read clock bus additionally comprises portions 120g and 122g, respectively, due to the necessary connection to the read clock generator 114, so that a clock signal output by the read clock generator 114 first has to pass the portions 120g and 124g, respectively, and experiences here a respective run time delay, before it enters with exactly that delay into the area of the read clock bus running in parallel to the data bus.
With reference to FIGS. 2 and 3, the problems underlying the prior art systems will be discussed in more detail. In FIG. 2, a portion of the memory system of FIG. 1 is illustrated, and here, as an example, the first memory element 108 of the second memory module 102, as well as a portion of the data bus 116 and a portion of the read clock bus 120. As is indicated by the arrows, the read clock (read_clock) is applied to the bus 120, while data (data) are read out on the bus 116 from the memory element 108, such as a DRAM.
The data read out from the memory element 108 will be sent in-phase to the read clock received at the memory element 108. If data are to be read from a memory element 108, the controller 112 initiates a respective instruction and data will be read out from the memory element according to the read clock. As can be seen from FIG. 2, data propagate from the memory element 108 via the portion 116d of the data bus 116 to the controller 112. Coming from the read clock generator 114, the read clock propagates via the portion 120g of the read clock bus 120 to the memory element 108 and concurrently to the portion 120h (see FIG. 2), which means further, into the direction of the controller 112. The read clock propagating to the memory element 108 initiates the readout there, does, however, need time tpd to reach the memory element from the node 120e via the portion 120f of the read clock bus 120. The incoming read clock initiates sending of data in the memory element 108, wherein these sent data again need time tpd to reach the data bus 116 from the memory element 108, so that the delay between read clock and data of 2xc3x97tpd shown in FIG. 3 arises. Thus, the read clock reaches the controller 112 prior to the data, by a time period 2xc3x97tpd earlier.
This delay has to be compensated by the controller 112, and solutions are known in the prior art where, due to the fact that the delay between the data signal (data) and the read clock signal (read_clock) is fixed, the controller 112 is designed to consider this delay internally. In order to ensure that, first, the occurring delay has to be detected and the whole system has to be calibrated, respectively. This procedure is, on the one hand, time intensive and expensive and, on the other hand, only secure for a short time due to the low stability of the calibration, so that the calibration procedures have to be repeated often. It is another disadvantage of this calibration procedure that it is susceptible with regard to short time interferences, such as cross talk on the data lines.
Starting from this prior art, the present invention is based on the object to provide an improved memory device where the delays between a data signal and a read clock signal in reading out the memory device will be minimized or eliminated.
The present invention is a memory device, having:
a memory module;
a controller;
a data bus connecting the controller and the memory module to read data from the memory module or write data into the memory module;
means for providing a read clock with which data are transferred from the memory module to the controller; and
a read clock bus, connecting means for providing a read clock, the memory module and the controller;
wherein means for providing a read clock is disposed in the memory module, so that the data bus and the read clock bus are substantially symmetric.
The present invention is based on the knowledge that the above-described problems in connection with the run times and the occurring delay between the data signal and the read clock signal at the controller can be avoided by compensating the asymmetry between the bus topologies.
According to the invention the xe2x80x9cglobalxe2x80x9d read clock generator is omitted, and a xe2x80x9clocalxe2x80x9d read clock generator is associated to each memory module instead. This leads to the fact, that in the inventive system, similar to a write operation in prior art systems, the read data signal propagates to the controller together with the read clock.
Due to the inventive arrangement of the read clock generators a symmetry of bus topologies arises, so that no time delay between the read data and the clock signal can be detected at the controller.
According to a preferred embodiment of the present invention, the memory module comprises a plurality of memory elements, wherein the data bus is divided into a plurality of sub-data buses and the read clock bus is divided into a plurality of sub-read clock buses, and wherein a sub-data bus and a sub-read clock bus are associated to each of the memory elements.
According to another preferred embodiment of the present invention, the memory device comprises a plurality of memory modules and a plurality of means for generating the read clock, wherein means for providing a read clock is associated to each memory module, and wherein the data bus connects the controller and the plurality of memory modules, and wherein the read clock bus connects the plurality of means for providing a read clock and the plurality of memory modules and the controller.
Preferably, the memory modules are DIMMs. Further, the memory elements preferably comprise DRAMs.